Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing
B. Sell, Seungchan An, Jeffrey L. Armstrong, David F. Bahr, B. Bains, R. Bambery, K. Bang, Dipanjan Basu, S. Bendapudi, D. Bergstrom, R. Bhandavat, S. Bhowmick, Markus J. Buehler, D. Caselli, S. Cekli, V. R. Saran Kumar Chaganti, Ying Chang, K. Chikkadi, T. Chu, Timothy F. Crimmins, Greg Darby, Canay Ege, P. Elfick, T. Elko-hansen, Sheng-Po Fang, Chaithanya Gaddam, M. Ghoneim, Hector Gomez, Sridhar Govindaraju, Z. Guo, W. Hafez, M. Haran, M. Hattendorf, Shiliang Hu, Abhishek Jain, S. Jaloviar, M. Jang, J. Kameswaran, V. Kapinus, A. Kennedy, Sabina Beranič Klopčič, D. Krishnan, J. Leib, Y.-T. Lin, N. Lindert, G. Liu, O. Loh, Yuxuan Luo, S. Mani, M. Mleczko, Supriya Mocherla, P. Packan, M. Paik, Ayushi Paliwal, R. Pandey, K. K. Patankar, Leonard C. Pipes, P. S. Plekhanov, C. Prasad, M. B. Prince, G. Ramalingam, R. Ramaswamy, J. Riley, Jose Roberto Sanchez Perez, J. Sandford, A. Sathe, F. Shah, Hyun‐Woo Shim, Srinath Subramanian, Shalabh Tandon, M. Tanniru, Dipto G. Thakurta, T. Troeger, Xielin Wang, C. Ward, Albert Welsh, S. Wickramaratne, Joshua D. Wnuk, S. Q. Xu, P. Yashar, J. Yaung, Kyung Jean Yoon, Na Young
Abstract
A new advanced CMOS FinFET technology, Intel 4, is introduced that extends Moore’s law by offering 2X area scaling of the high performance logic library and greater than 20% performance gain at iso-power over Intel 7. The scaled high-performance library offers 50nm gate pitch, 30nm fin pitch and 30nm minimum metal pitch. This node delivers 8VT (4NVT + 4PVT) spanning a range of 190mV/180mV for N/PMOS, enabling designers to choose between power and speed requirements. EUV lithography is used extensively to simplify the process flow and improve yield. The interconnect stack features 16 metal layers with enhanced copper metallurgy at critical lower layers to deliver improved electromigration (EM) and lower line resistance (LR).