Forming-free and Annealing-free V/VO<sub>x</sub>/HfWO<sub>x</sub>/Pt Device Exhibiting Reconfigurable Threshold and Resistive switching with high speed (<30ns) and high endurance (>10<sup>12</sup>/>10<sup>10</sup>)
Yaoyao Fu, Yue Zhou, Xiaodi Huang, Bin Gao, Yuhui He, Yi Li, Yang Chai, Xiangshui Miao
Abstract
For the first time, we experimentally demonstrated the fully reconfigurable switching between selector and RRAM in one V/VO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> /HfWO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> /Pt device while with no electroforming or high-temperature annealing processes during fabrication. In the same device: (1) Ultra-high endurance (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> ), high operation speed (<30ns) and excellent threshold stability (variation <5.7%) are demonstrated in the selector mode which is attributed to threshold switching (TS) characteristics of VO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> ; (2) High on-off ratio (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ), high endurance (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> ) and reduction of the leakage current with two orders of magnitude are achieved in the RRAM mode resulted from resistive switching (RS) characteristics of HfWO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> . These reproducible volatile and non-volatile switching properties are further utilized to emulate electronic neurons and synapses, respectively, and in this way the V/VO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> /HfWO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> /Pt-based fully memristive spiking neural network can be realized at a dramatically reduced lentency (∼500 ns) and power consumption (∼10 fJ/per operation for one synapse).