DES encryption and decryption algorithm implementation based on FPGA
Subhi R. M. Zeebaree
Abstract
Nowadays there is a lot of importance given to data security on the internet. The DES is one of the most preferred block cipher encryption/decryption procedures used at present. This paper presents a high throughput reconfigurable hardware implementation of DES Encryption algorithm. This achieved by using a new proposed implementation of the DES algorithm using pipelined concept. The implementation of the proposed design is presented by using Spartan-3E (XC3S500E) family FPGAs and is one of the fastest hardware implementations with much greater security. At a clock frequency of 167.448MHz for encryption and 167.870MHz for decryption, it can encrypt or decrypt data blocks at a rate of 10688Mbps.
Topics & Concepts
EncryptionComputer scienceBlock cipherField-programmable gate arrayBlock (permutation group theory)ThroughputEmbedded systemDisk encryption hardwareEncryption softwareCryptography56-bit encryptionComputer hardwareDisk encryption theory40-bit encryptionMultiple encryptionDisk encryptionAlgorithmPublic-key cryptographyComputer networkAttribute-based encryptionOperating systemMathematicsGeometryWirelessCryptographic Implementations and SecurityChaos-based Image/Signal EncryptionCoding theory and cryptography