Analysis of Power, Delay and SNM of 6T & 8T SRAM Cells
Vibhash Choudhary, Dharmendra Singh Yadav
Abstract
6T and 8T SRAM cells have been compared on 180nm technology using an industry-standard Cadence Virtuoso Tool. It's challenging to make an SRAM cell with low power consumption and stay in a small space. The consumption of power on both the SRAM cells are compared. The parameters of SRAM Static Noise Margin (SNM), Write Delay, Read Delay and average power consumption are examined and discussed thoroughly. Results illustrate that Read delay and Write delay will decrease of 8T as differentiate to 6T SRAM. Effect of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf> on average power consumption and delay is further highlighted in the present paper. These comparisons then can provide a vision to designers for finding an optimal supply voltage for a particular design while minimizing the design to process variation.