Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques
Xiyuan Tang, Jiaxin Liu, Yi Shen, Shaolan Li, Linxiao Shen, Arindam Sanyal, Kareem Ragab, Nan Sun
Abstract
This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.
Topics & Concepts
Successive approximation ADCComparatorConvertersElectronic engineeringComputer sciencePower (physics)Block (permutation group theory)Capacitive sensingElectrical engineeringEngineeringVoltageMathematicsGeometryQuantum mechanicsPhysicsAnalog and Mixed-Signal Circuit DesignAdvancements in Semiconductor Devices and Circuit DesignLow-power high-performance VLSI design