Design and Optimization of 4-Bit Array Multiplier with Adiabatic Logic Using 65 nm CMOS Technologies
Divya Sharma, Amrita Rai, Sunita Debbarma, Om Prakash, Mukesh Kumar Ojha, Vijay Nath
Abstract
This paper proposes a 4-bit array multiplier useful in the design of basically mixer circuit, which is highly involved in signal and image processing using an efficient low-power VLSI technique. The presented architecture is completely implemented adiabatic techniques in the Near Threshold Region, which optimize the product of propagation delay and power dissipation. Multiplier is the most frequently used element in many digital electronics applications. Depending on the applications, various types of multipliers emerge. With this technique, the total power dissipation, i.e. dynamic power dissipation as well as static power dissipation is less as compared to the conventional CMOS technique. The Near Threshold Adiabatic Logic (NTAL) technique is used with a single timevarying power supply which reduces the clock tree management and enhances the energy-saving capability. Simulation of the proposed design is done by Cadence virtuoso schematic editor with specter simulator on TSMC 65 nm technology node to verify the optimized result. Also comparing our result to conventional CMOS techniques with all the same design parameters, the result shows that power dissipation improvement of approximately 66.6%, 14.4%, and 64.6% with respect to varying frequency, supply voltage, and load capacitance with other parameters keep constant such as if the frequency is varying than capacitance load value is Cload = 10 pF and VDD(max) = 1.2 V, similarly if the supply voltage is varying than capacitance load value is Cload = 10 pF and frequency F = 4 GHz and if load capacitance is varying than frequency F = 4 GHz and supply voltage VDD(max) = 1.2 V.