Selective operations of multi-pillar SOT-MRAM for high density and low power embedded memories
Kaiming Cai, S. Van Beek, Siddharth Rao, Kaiquan Fan, Mohit Gupta, V.D. Nguyen, Ganesh Jayakumar, Giacomo Talmelli, Sébastien Couet, Gouri Sankar Kar
Abstract
We demonstrate a multi-pillar (MP) spin-orbit torque (SOT)-MRAM concept, which enables lower write current and high-density integration. We experimentally demonstrate the selective write operation of multi-bits in CMOS-compatible 300mm integrated top-pinned perpendicular MTJs. Multiple MTJs on a shared SOT track can be individually selected by gate voltages and independently switched by sub-ns pulses with 30% reduction in operation current. Our concept of selective operations with less transistors and lower writing energy will significantly enhance the density and energy efficiency of SOT-MRAM.