System in package embedding III-V chips by fan-out wafer-level packaging for RF applications
Arnaud Garnier, Laetitia Castagné, F. Greco, Thomas Guillemet, Laurent Marechal, Mehdy Neffati, Rémi Franiatte, P. Coudrain, S. Piotrowicz, Gilles Simon
Abstract
This paper deals with the packaging of two III-V chips combined to form a System-in-Package (SiP) for RF base transceiver station applications. The first die consists of a high-power amplifier (HPA) and a switch made on GaN-on-SiC. The second one features a low-noise amplifier (LNA) and a driver built on GaAs. Both chips bring together the best of each substrate technology, namely high RF and power performances of GaN, and low-noise capability of GaAs. The SiP was built using fan-out wafer-level packaging (FOWLP) in chip-first face-down configuration. The gap between the chips is as low as 100 μm. Electrical routing is secured by redistribution layer (RDL) and balls for flip-chip assembly on the PCB. Thermal dissipation has to be managed opposite to the PCB to avoid a too complex PCB design. It is managed by directly contacting the HPA backside with a Cu-liner acting as a heat spreader. This is achieved by opening the molding compound using laser ablation, and subsequently plating Cu on the SiP backside. The SiP has a final size of 4×4×0.35 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> , which eventually aims at fitting into the meshing size imposed by an active antenna array operating at 28 GHz. This paper addresses GaN and GaAs chips specific features which have an impact for the FOWLP process flow: low thickness ( ~ 100 μm) relative to the targeted 350 μm-thick molding compound; chips backside coated with Au which shall not be removed; chip frontside with a relatively high topology (almost 20 μm). Signal losses were measured in an SiP-like environment at 0.1 dB/mm, 0.2 dB/mm and 0.4 dB/mm respectively at 30 GHz, 40 GHz and 60 GHz. These results are promising in anticipation of the SiP final testing.