Hardware Design for the Affine Motion Compensation of the VVC Standard
Marcello M. Muñoz, Denis Maass, Murilo Perleberg, Luciano Agostini, Marcelo Porto
Abstract
The Affine Motion Estimation (AME) of the Versatile Video Coding (VVC) standard is a high-complexity task. The AME requires Affine Motion Compensation (MC) to be performed for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4\times 4$</tex> subblocks, where the Motion Vector relative to the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4\times 4$</tex> subblock is adopted to define which of the 15 6-tap interpolation filters should be used to interpolate each sample of the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4\times 4$</tex> subblock. This work presents a dedicated hardware implementation for the Affine MC of the VVC standard, where the ASIC synthesis results for this architecture for TSMC 40nm standard cells show an area requirement of 97.5k gates and power dissipation of 11.1mW when targeting the processing of 4K Ultra-High Definition (UHD) video at a frequency of 808MHz. To the best of the author's knowledge, this work presents the first hardware implementation of the VVC Affine MC in the literature.