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Fast and Accurate Wire Timing Estimation Based on Graph Learning

Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, Longxing Shi

202323 citationsDOI

Abstract

Accurate wire timing estimation has become a bottleneck in timing optimization since it needs a long turn-around time using a sign-off timer. The gate timing can be calculated accurately using lookup tables in cell libraries. In comparison, the accuracy and efficiency of wire timing calculation for complex RC nets are extremely hard to trade-off. The limited number of wire paths opens a door for the graph learning method in wire timing estimation. In this work, we present a fast and accurate wire timing estimator based on a novel graph learning architecture, namely GNNTrans. It can generate wire path representations by aggregating local structure information and global relationships of whole RC nets, which cannot be collected with traditional graph learning work efficiently. Experimental results on both tree-like and non-tree nets demonstrate improved accuracy, with the max error of wire delay being lower than 5 ps. In addition, our estimator can predict the timing of over 200K nets in less than 100 secs. The fast and accurate work can be integrated into incremental timing optimization for routed designs.

Topics & Concepts

BottleneckEstimatorComputer scienceTimerStatic timing analysisGraphAlgorithmPath (computing)Theoretical computer scienceMathematicsEmbedded systemStatisticsProgramming languageMicrocontrollerVLSI and FPGA Design TechniquesVLSI and Analog Circuit TestingLow-power high-performance VLSI design
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