Analysis and Design of Dual-Peak G<sub>max</sub>-Core CMOS Amplifier in D-Band Embedding a T-Shaped Network
Jiseul Kim, Chan-Gyu Choi, Kangseop Lee, Kyunghwan Kim, Seung-Uk Choi, Ho-Jin Song
Abstract
In order to overcome the performance limitation of CMOS technology at high frequencies above 100 GHz, the concept of maximum achievable gain (G <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> ) with an embedding network has been investigated. In this work, a novel G <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> -core embedding a T-shaped gain-boosting network that provides two G <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> -peaks is analyzed and demonstrated in the D-band with a 28-nm FD-SOI CMOS process. With the proposed topology, one can design the peak G <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> frequencies and in/output impedances simultaneously as desired for high gain and broadband operation. The fabricated amplifier offers a peak small-signal gain and bandwidth of 14.5 dB and 26 GHz, respectively, with power consumption of 21.6 mW in 117 - 143 GHz.