Desing of VLSI Architecture for a flexible testbed of Artificial Neural Network for training and testing on FPGA
Prajwal Shetty, Rahul Kudtarkar, Siddesh Naik, A. Abhilash, Ayash Ashraf, Shazia Ashraf, Navaid Zafar Rizvi, Shakeel Ahmad Dar, Jhin-Fang Huang, Cheng-Ku Hsieh, Meng Yu, Lipeng Wu, Fule Li, Zhihua Wang, Yonghong Tao, Yong Lian, Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, U Seng-Pan, Rui, Paulo Martins, Franco Maloberti, Brian Ginsburg, Anantha Chandrakasan, K Krishna, T Lokesh, Ramashri, Pieter Harpe, Cui Zhou, Yu Bi, Nick Van Der Meijs, Xiaoyan Wang, Kathleen Philips, Guido Dolmans, Harmke De, Groot, Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro, Wang Ya, Xue Chunying, Li Fule, Zhang Chun, Wang Zhihua, Harshit Dosi, Rekha Agrawal, Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, U Seng-Pan, Rui, Paulo Martins, Franco Maloberti, Young-Ju Kim, Hee-Cheol Choi, Si-Wook Yoo, Seung-Hoon Lee, Dae-Young Chung, Kyoung-Ho Moon, Ho-Jin Park, Jae-Whui Kim, Mounir Boulemnakher, Eric Andre, Jocelyn Roux, Frederic Paillardet, Yasuhide Shimizu, Shigemitsu Murayama, Kohhei Kudoh, Hiroaki Yatsuda, Chun Lee, Michael Flynn
Abstract
The creation of an 8-bit SAR ADC with a 0.8V and 5V input voltage is discussed in the publication. Cadence Virtuoso software was used to implement the design, which made use of both 180nm and 90nm technology. The comparator block, which was created using Verilog code and required to operate properly, was the main emphasis of the design. Since the comparator is the block that uses the most power overall, optimising it took up a sizable chunk of the design process. The DAC sub-block was implemented using an MDAC network to increase the ADC's accuracy. The ADC was driven by asynchronous control logic, which was implemented using Verilog code and did not require a clock signal.