Optimized programming algorithms for multilevel RRAM in hardware neural networks
Valerio Milo, Francesco Anzalone, Cristian Zambelli, Eduardo Pérez, Mamathamba Kalishettyhalli Mahadevaiah, Óscar G. Ossorio, P. Olivo, Christian Wenger, Daniele Ielmini
Abstract
A key requirement for RRAM in neural network accelerators with a large number of synaptic parameters is the multilevel programming. This is hindered by resistance imprecision due to cycle-to-cycle and device-to-device variations. Here, we compare two multilevel programming algorithms to minimize resistance variations in a 4-kbit array of HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> RRAM. We show that gate-based algorithms have the highest reliability. The optimized scheme is used to implement a neural network with 9-level weights, achieving 91.5% (vs. software 93.27%) in MNIST recognition.