Compact modeling of 3D vertical junctionless gate-all-around silicon nanowire transistors towards 3D logic design
C. Mukherjee, Arnaud Poittevin, Ian O’Connor, Guilhem Larrieu, Cristell Maneux
Topics & Concepts
TransistorNanowireSilicon nanowiresLogic gateMaterials scienceElectronic circuitScalingAND gateNanotechnologyElectronic engineeringOptoelectronicsComputer scienceElectrical engineeringEngineeringVoltageGeometryMathematicsSemiconductor materials and devicesAdvancements in Semiconductor Devices and Circuit DesignSilicon Carbide Semiconductor Technologies