Improving Memory Reliability by Bounding DRAM Faults
Kjersten Criss, Kuljit Bains, Rajat Agarwal, Tanj Bennett, Terry Grunzke, Jangryul Keith Kim, Hoeju Chung, Munseon Jang
Abstract
DRAM reliability is an increasingly difficult to address as error correction code (ECC) overhead increases and process nodes shrink, driving up DRAM cell errors. As single bit errors increase, failures of larger hardware structures within the memory are also an ever-present threat to data integrity.
Topics & Concepts
DramComputer scienceReliability (semiconductor)Reliability engineeringEmbedded systemError detection and correctionOverhead (engineering)Bounding overwatchData retentionProcess (computing)Random access memoryDynamic random-access memoryCode (set theory)Memory errorsComputer hardwareSemiconductor memoryOperating systemEngineeringAlgorithmRecallComputer securityProgramming languageArtificial intelligenceLinguisticsPower (physics)Set (abstract data type)PhysicsPhilosophyQuantum mechanicsRadiation Effects in ElectronicsSemiconductor materials and devicesAdvancements in Semiconductor Devices and Circuit Design