Implementation of Boolean and Arithmetic Functions with 8T SRAM Cell for In-Memory Computation
Anil Rajput, Manisha Pattanaik
Abstract
The current computing system based on von-Neumann architecture is facing a memory wall, power wall, instruction parallelism wall. These walls of the current computing system have been a significant impact on computing efficiency of computing systems in the present time due to high prominence on Data insensitive applications. Computation In Memory (CIM) architecture is one of the emerging architecture for computation to break these three walls. In this paper, we present an In memory computational methodology and arithmetic circuit co- designs using 8T SRAM cell. The boolean logic operation and arithmetic functions are demonstrated with 8T SRAM cell in 180 nm CMOS technology. The NAND, AND, NOR, OR boolean logics are demonstrate using 8T SRAM cells with the proposed sensing scheme to verifying the In-Memory computations ability of 8T SRAM cells. This proposed sensing scheme with 8T SRAM cell provides an energy improvement of 26.4% over 8+T SRAM based IMC and also offer a high sense margin of NAND operation. Finally, for implementation of the arithmetic circuit, SRAM memory array has to be designed using the 8T SRAM cell and proposed sensing scheme and mapped half adder and half subs tractor NOR net-list into SRAM memory array and verify their functionality.