Foundry Monolithic 3D BEOL Transistor + Memory Stack: Iso-performance and Iso-footprint BEOL Carbon Nanotube FET+RRAM vs. FEOL Silicon FET+RRAM
Tathagata Srimani, A. C. Yu, Robert M. Radway, D. Rich, Matthew D. Nelson, S.S. Wong, David Murphy, Samuel H. Fuller, Gage Hills, Subhasish Mitra, Max M. Shulaker
Abstract
We show, for the first time, a BEOL carbon nanotube FET (CNFET) + Resistive RAM (RRAM) stack through monolithic 3D (M3D) integration, directly over silicon (Si) CMOS, that achieves comparable performance (read power write energy/latency, endurance, retention, multiple bits-per-cell capability) in the same footprint as conventional RRAM stack using FEOL Si FET access transistors. This process is established within SkyWater Technology Foundry (90/130nm technology node on 200mm Si wafers), and an apples-to-apples comparison is made versus FEOL Si FET+RRAM fabricated on the same wafers, from the same foundry, at the same node. Such BEOL CNFET+RRAM technology unlocks a large architecture design space with significant system-level energy-delay product (EDP) benefits vs. FEOL Si+RRAM-only designs, e.g., $\gt 5 \times $ EDP benefits for new iso-footprint, iso-memory-capacity M3D architectures uniquely enabled by our M3D physical design. Our BEOL CNFET+RRAM therefore creates a new and complementary integration path for dramatically improving system-level energy and delay, iso-node and iso-footprint.