High-Performance and Soft Error Immune Spintronic Retention Latch for Highly Reliable Processors
Abdolah Amirany, Kian Jafari, Mohammad Hossein Moaiyeri
Abstract
Radiation vulnerability and high power consumption are critical challenges in the modern CMOS processors. Magnetic tunnel junction also known as MTJ is an emerging spintronic devices and one of the promising choices for answering these challenges thanks to their fascinating properties such as radiation immunity, non-volatility, high endurance and compatibility with conventional CMOS transistors fabrication process. Utilize the fascinating properties of the MTJ, a high performance and low power soft error immune retention latch proposed in this paper. Thanks to the single event upset (SEU) immunity, the proposed latch is applicable in designing highly reliable processors. Because of the novel design of the proposed latch, the MTJ switching delay does not affect the performance of the design. Simulation results strongly indicate that the proposed latch outperforms the previous design when considering delay, power, and power delay product (PDP).