Loop Dynamics Analysis of PAM-4 Mueller–Muller Clock and Data Recovery System
Kunal Yadav, Ping-Hsuan Hsieh, Anthony Chan Carusone
Abstract
This paper provides a framework for analyzing the loop dynamics of the clock and data recovery (CDR) system of ADC-based PAM-4 receivers, which will assist in extending the timing recovery loop bandwidth. This paper formulates an accurate linear model of linear and signed Mueller–Muller phase detector for baud-rate clock recovery. Different equalization configurations of continuous-time linear equalizer (CTLE) and feed-forward equalizer (FFE) are evaluated from a phase detector performance perspective to enable high CDR loop bandwidth. The impact of loop latency on the timing recovery of ADC-based PAM-4 receivers is also analyzed and demonstrated using accurate behavioral simulations. The analysis and behavioral results show that, to achieve high CDR loop bandwidth with a good jitter tolerance, the phase detector gain to noise ratio should be maximized, and CDR loop latency should be minimized.