Vertically-Stacked Si<sub>0.2</sub>Ge<sub>0.8</sub> Nanosheet Tunnel FET With 70 mV/Dec Average Subthreshold Swing
Ryoongbin Lee, Junil Lee, Kitae Lee, Soyoun Kim, Hyunho Ahn, Sihyun Kim, Hyun‐Min Kim, Changha Kim, Jong‐Ho Lee, Sangwan Kim, Byung‐Gook Park
Abstract
A novel CMOS-compatible SiGe Tunnel Field-Effect Transistor (TFET) with a high current drivability is demonstrated, which features a vertically-stacked SiGe nanosheet (NS) with high Ge content and gate-all-around(GAA) structure to improve carrier injection efficiency and gate controllability. A multi-NS Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.2</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.8</sub> channel is formed by the Si selective etching and Ge condensation technique. The measured data shows both the 50 mV/dec minimum subthreshold swing (SS) and 70 mV/dec average SS over 3 decades of drain current change. Compared to previously reported devices, it is clear that the proposed SiGe nanosheet TFET can achieve steeper switching and low-level leakage current with a low drive voltage as an alternative to conventional MOSFET.