Engineering MoSe2/MoS2 heterojunction traps in 2D transistors for multilevel memory, multiscale display, and synaptic functions
Yeonsu Jeong, Han Joo Lee, Jun-Kyu Park, Sol Lee, Hye‐Jin Jin, Sam Park, Hyunmin Cho, Sungjae Hong, Taewook Kim, Kwanpyo Kim, Shinhyun Choi, Seongil Im
Abstract
Abstract We study a low voltage short pulse operating multilevel memory based on van der Waals heterostack (HS) n-MoSe 2 /n-MoS 2 channel field-effect transistors (FETs). Our HS memory FET exploited the gate voltage (V GS )-induced trapping/de-trapping phenomena for Program/Erase functioning, which was maintained for long retention times owing to the existence of heterojunction energy barrier between MoS 2 and MoSe 2 . More interestingly, trapped electron density was incrementally modulated by the magnitude or cycles of a pulsed V GS , enabling the HS device to achieve multilevel long-term memory. For a practical demonstration, five different levels of drain current were visualized with multiscale light emissions after our memory FET was integrated into an organic light-emitting diode pixel circuit. In addition, our device was applied to a synapse-imitating neuromorphic memory in an artificial neural network. We regard our unique HS channel FET to be an interesting and promising electron device undertaking multifunctional operations related to the upcoming fourth industrial revolution era.