On‐Chip Integrated High Gain Complementary MoS<sub>2</sub> Inverter Circuit with Exceptional High Hole Current P‐Channel Field‐Effect Transistors
Zichao Ma, Cristine Jin Estrada, Kui Gong, Lining Zhang, Mansun Chan
Abstract
Abstract Integration of complementary logic circuits using 2D layered MoS 2 can overcome the fundamental device limitations of silicon‐based Complementary metal–oxide–semiconductor (CMOS) technology. For the high functionality of complementary MoS 2 logic circuits, realizing high‐current p‐channel MoS 2 field‐effect transistors (p‐FETs) is essential yet quite challenging. Herein, passivation of surface defects of MoS 2 by atomic oxygen is proposed theoretically by ab initio simulations in favor of mitigating the Fermi level pinning. Experimentally, an atomic layer passivation (ALP) technique combined with a slow metal‐deposition strategy is developed to reduce contact resistance to p‐channel MoS 2 and report a more than tenfold increase in the contact hole conductance. The fabricated p‐channel MoS 2 FETs achieve a record high saturation current of 45 µA µm −1 with a 0.7 µm channel length under a V DS of −1 V. With these techniques, an electron–hole pairing in MoS 2 similar to the Si counterpart is achieved for complementary circuit applications. An on‐chip integrated MoS 2 inverter with Pt electrodes is demonstrated with a high gain of 20 at 3 V supply.