Pareto Optimal Characterization of a Microwave Transistor
Filiz Güneş, Ahmet Uluslu, Peyman Mahoutı
Abstract
Herein, noise, gain and port mismatchings of a microwave small-signal transistor are expressed as all the set of acceptable Pareto optimal solutions and trade-off relations within the device operation (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> , I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> ,f) domain without any need of expert knowledge of microwave device. In this multi-objective optimization problem, non-dominated sorting genetic algorithm (NSGA) -III is applied to an ultra-low noise amplifier (LNA) transistor NE3511S02 (HJ-FET) where the noise F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">req</sub> ≥ F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> and output mismatching V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">outreq</sub> ≥ 1 are preferred as the reference points, while the input mismatching V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inopt</sub> ≥ 1 and gain GTmax are optimized with respect to source ZS and load ZL within the unconditionally stable working area. Thus, diverse set of the Pareto optimal (the required noise F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">req</sub> , the optimum input V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inopt</sub> , the required output V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">outreq</sub> , the maximum transducer gain G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Tmax</sub> ) quadruples are resulted from a fast search of the solution space. Furthermore, the optimum bias condition (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> , I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> ) and sensitivities of the terminations to fabrication tolerances are also determined using the cost analysis in the operation domain for the required P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> , I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DSmax</sub> and performance quadruple. Finally, this work is expected to enable a designer to provide the feasible design target space (FDTS) consisting of all trade-off relations among all the transistor's performance ingredients to be used in the challenging LNA designs.