20.1 A High Common-Mode Transient Immunity GaN-on-SOI Gate Driver for High dV/dt SiC Power Switch

Abstract

Silicon carbide (SiC) MOSFET devices offer better performance in high-voltage (HV) and high-current applications, such as electric vehicles, railways, and motor drives due to their low losses, low impedance, high blocking voltage, and good high temperature tolerance. Recently, the rated 1700V SiC is used in a power conversion system (PCS) for efficient energy storage. Compared to 800V and 1200V SiCs, high voltage and fast switching SiC MOSFET will cause large dv/dt (> 100kV/µs) and di/dt <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(&gt;10\text{kA}/\mu\mathrm{s})$</tex> High dv/dt at the switch node will couple the common mode transient (CMT) disturbances to the high side transmitter (TX) through an isolation barrier parasitic capacitance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{C}_{\text{PAR}}$</tex> . Meanwhile, a large di/dt on the parasitic inductance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{L}_{\text{PAR}}$</tex> will cause abnormal ringing and couple to the TX through <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{C}_{\text{PAR}}$</tex> (upper left of Fig. 20.1.1). Although the isolated gate drivers (IGD) with the transformer galvanic isolation have good common-mode transient immunity (CMTI) [1], their duty cycle is limited to 50% due the regeneration of the drive voltage being controlled by the duty cycle [2]. In contrast, capacitive isolation is not limited by the duty cycle, but instead, requires the modulator at the TX circuit to transmit the drive signal. When CMT disturbance occurs, a common mode current <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{I}_{\text{CM}})$</tex> , proportional to dv/dt at the switching node, flows through <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{C}_{\text{PAR}}$</tex> to the TX circuit and affects the conventional demodulation circuit of the receiver (RX) circuit (top in Fig. 20.1.1). The dv/dt ranges from over <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$100\text{kV}/\mu\mathrm{S}$</tex> for 1700V SiC to 40kV/µs for 800V SiC. In the case of large <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{R}_{1(2)}$</tex> , the induced <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}_{\text{CM}}$</tex> will cause large common-mode shift <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{CMS}=\mathrm{I}_{\text{CM}}\ ^{\star}\mathrm{R}_{1(2)})$</tex> . A large CMS can cause the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{IP}}$</tex> or <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{IN}}$</tex> of the comparator in the demodulator to exceed the input common mode range (ICMR) and the demodulator cannot receive the correct control signal for some CMT periods. Due to the absence of correct control signals, fault tolerance mechanisms can limit the runtime within a hysteresis window [3]. However, under high voltage, the noise coupling to the gate of the low-side SiC MOSFET, through the gate-to-drain capacitance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{C}_{\text{GD}}$</tex> , will become larger due to the higher dv/dt, which will increase the possibility of abnormal turn-on. State-of-the-art gate drivers require an external negative supply voltage, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{EE}}$</tex> to turn off the SiC MOSFET to suppress abnormal turn-on. In addition, conventional discrete <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{EE}}$</tex> voltage sources are set more negative to overcome discrete parasitic resistance effects. However, efficiency is reduced if <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{EE}}$</tex> is too low.

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