Analysis and Design of Multi-Stacked FET Power Amplifier With Phase-Compensation Inductors in Millimeter-Wave Band
Kyung-Hwan Kim, Inho Choi, Kangseop Lee, Seung-Uk Choi, Jiseul Kim, Chan-Gyu Choi, Ho-Jin Song
Abstract
Stacked-FET topology is analyzed to increase the output power of a power amplifier (PA) in the millimeter-wave (mm-wave) band. In the mm-wave band, parasitic capacitances of the transistor severely degrade stacking efficiency due to the phase mismatch between stacked FETs. The phase-compensation (PC) inductances, including the losses of the inductor for the best stacking efficiency, are presented in both series and shunt connections. From this analysis, a triple-stacked-FET PA is designed in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$F$ </tex-math></inline-formula> -band. Proper PC series or shunt inductor types are used between the first and second stacked FETs and between the second and third stacked FETs in consideration of the core layout and inductor size. The PA is fabricated in the 28-nm CMOS fully depleted silicon-on-insulator (FD-SOI) process. With a compact core area of 0.054 mm2, the PA achieves peak <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {SAT}}$ </tex-math></inline-formula> and PAEMAX of 15.1 dBm and 18.6%, respectively.