A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-nand Technology and Featuring a 23.3 Gb/mm <sup>2</sup> Bit Density
A. Khakifirooz, Eduardo Anaya, Sriram Balasubrahmanyam, Geoff Bennett, Daniel Castro, John Egler, Kuangchan Fan, Rifat Ferdous, Kartik Ganapathi, Omar Guzmán, Changwan Ha, Rezaul Haque, Vinaya Harish, Majid Jalalifar, O. Jungroth, Sung-Taeg Kang, Golnaz Karbasian, Jee-Yeon Kim, Siyue Li, Aliasgar S. Madraswala, Srivijay Maddukuri, Amr Mohammed, Shanmathi Mookiah, Shashi Nagabhushan, Binh Ngo, Deep Patel, Sai Kumar Poosarla, Naveen V. Prabhu, Carlos Quiroga, Shantanu Rajwade, Ahsanur Rahman, Jalpa Shah, Rohit S. Shenoy, Ebenezer Tachie Menson, Archana Tankasala, Sandeep Krishna Thirumala, Sagar Upadhyay, Krishnasree Upadhyayula, Ashley Velasco, Nanda Kishore Babu Vemula, Bhaskar Venkataramaiah, Jiantao Zhou, B. Pathak, Pranav Kalavade
Abstract
We present the industry’s first 5b/cell (PLC) NAND chip, fabricated in a 192-layer floating-gate (FG) technology. With a die capacity of 1.67 Tb and an area of 73.3 mm2, it delivers a record bit density of 23.3 Gb/mm2. Key innovations to enable reliable PLC operation and the features implemented to support system-level usage are described. These include: a fast soft-bit read algorithm capable of handling the presence of defective bitlines; a fast read-calibration algorithm; a reverse-read waveform to improve the read margin; SLC-write-through; and program suspend and resume algorithm compatible with the above read operations.