Coordination of Solid-State Circuit Breakers for DC Grids Under High-Fault-di/dt Conditions
Govind Chavan, Xiaoqing Song, Debanjan Chatterjee, Abhinav Patni, Pietro Cairoli
Abstract
The protection of DC grids is challenging due to the lack of natural current zero-crossing and the small parasitic inductances that lead to high fault di/dt. Solid-state circuit breakers (SSCBs) have several advantages over conventional mechanical circuit breakers in this regime: rapid fault clearing speeds, arc-less current interruption, and low peak-fault-current making them suitable for DC system protection. SSCBs can lower the peak-fault-current, which is beneficial for the system; however, it also creates new challenges for the protection coordination of SSCBs as the tripping curve of SSCBs with different current ratings are closer to each other due to the lower peak fault current. This could cause the unnecessary tripping of the upstream SSCBs in the DC grid infrastructure. This paper investigates the limits on coordinating multiple SSCBs under extremely high fault-di/dt conditions and establishes guidelines for the selection of SSCBs in the DC network.