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A 1.1μs 1.56Gb/s/mm<sup>2</sup> Cost-Efficient Large-List SCL Polar Decoder Using Fully-Reusable LLR Buffers in 28nm CMOS Technology

Dongyun Kam, Byeong Yong Kong, Youngjoo Lee

20222022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)15 citationsDOI

Abstract

This paper presents a cost-efficient large-list SCL polar decoder supporting an ultra-reliable channel coding in 5G and beyond communications. To minimize huge implementation costs, the proposed design utilizes fully-reusable LLR buffers associated with stage unfolding and LLR overwriting schemes, significantly reducing the on-chip buffer overheads by 67% compared to the state-of-the-art decoder. Implemented in a 28nm CMOS, the prototype list-8 decoder achieves 1.1μs and 1.56Gb/s/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> to decode a 1024b 5G polar codeword while providing the ultra-reliable error-correcting performance.

Topics & Concepts

CMOSDecoding methodsComputer scienceCode wordPolarCoding (social sciences)Polar codeComputer hardwareChannel (broadcasting)Error detection and correctionEmbedded systemAlgorithmElectronic engineeringTelecommunicationsPhysicsEngineeringMathematicsAstronomyStatisticsError Correcting Code TechniquesAdvanced Wireless Communication TechniquesCoding theory and cryptography
A 1.1μs 1.56Gb/s/mm<sup>2</sup> Cost-Efficient Large-List SCL Polar Decoder Using Fully-Reusable LLR Buffers in 28nm CMOS Technology | Litcius