STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application
Siddharth Rao, W. Kim, S. Van Beek, Shreya Kundu, Manu Perumkunnil, Stefan Cosemans, Faisal Mohd-Yasin, Sébastien Couet, R. Carpenter, Barry O’Sullivan, Shamin Houshmand Sharifi, N. Jossart, Laurent Souriau, L. Goux, D. Crotti, Gouri Sankar Kar
Abstract
We present a detailed study of the impact of damage minimizing patterning schemes on the electrical performance of perpendicular STT-MRAM devices at array level, compatible with 22 nm CMOS technology node. By employing a novel patterning scheme involving physical ion beam etch (IBE), etchback and oxidation steps, we show reduction in switching voltage (32%), switching energy (20%) and an improvement in the reliability window (20%), as compared to the conventional physical etch. These improvements are reported in conjunction with 10-year data retention (Δ), WER ~ 1 ppm and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> cycling on 1 kbit cells. We attribute these improvements to a significant reduction in free layer (FL) damage. Morphological studies highlighting the minimization of oxygen penetration and the subsequent bird's beak formation around the FL strongly support our understanding. These results highlight a possible tuning knob in the IBE process to improve the device performance significantly and may help to improve the tail bits.