High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications
Mitul Sudhirkumar Nagar, Aditya Mathuriya, Sohan H. Patel, Pinalkumar Engineer
Abstract
Among various platforms for computer vision algorithms, FPGA has gained popularity as a low-power solution. These algorithms involve convolution operation which are extensively performed using signed multipliers. Hence, this work proposes high-speed and energy-efficient signed fixed-point multipliers for digital signal processing (DSP) applications. This work focuses on reducing the CPD using LUT-based Booth radix-4 partial product (PP) generation with Bewick’s sign extension and Dadda-based concurrent PP reduction with carry save adder (CSA) for Xilinx (now AMD) FPGA. The proposed design eliminates the requirement of a long carry chain for PP reduction. The proposed multiplier reduces combinational path delay (CPD) by 3%, 4%, and 16% compared to the state-of-the-art (SoA) multiplier for 8×8, 16×16, and 32×32 sizes, respectively. We have also analyzed our proposed 32×32 multiplier by pipelining, which offers CPD and EDP reduction by 12.28% and 19.47% at the cost of a 3% and 80% increase in LUTs and flip-flops, respectively, compared to the combinatorial multiplier.