A Hardware-Oriented Echo State Network and its FPGA Implementation
Kentaro Honda, Hakaru Tamukoh
Abstract
This paper proposes implementation of an Echo State Network (ESN) to Field Programmable Gate Array (FPGA). The proposed method is able to reduce hardware resources by using fixed-point operation, quantization of weights, which includes accumulate operations and efficient dataflow modules. The performance of the designed circuit is verified via experiments including prediction of sine and cosine waves. Experimental result shows that the proposed circuit supports to 200 MHz of operation frequency and facilitates faster computing of the ESN algorithm compared with a central processing unit.
Topics & Concepts
Echo (communications protocol)Field-programmable gate arrayComputer scienceState (computer science)Embedded systemComputer hardwareComputer architectureComputer networkProgramming languageNeural Networks and Reservoir ComputingNeural Networks and ApplicationsAdvanced Memory and Neural Computing