29.7 A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS
Chi-Hsiang Huang, Xun Sun, Yidong Chen, Rajesh Pamula, Arindam Mandal, Visvesh Sathe
Abstract
Single-inductor multiple-output (SIMO) converters present a promising technology for enabling fine-grained supply-voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> ) domains in SoCs. With efficiencies approaching those of buck converters, SIMO converters allow multiple domains to share a single inductor, thus reducing the use of bulky passive components [1-5]. However, SIMO converters suffer from a poor transient response and significant ripple, requiring extensive V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> margining. Operation at an elevated V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> -and, therefore, the load-current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">load</sub> )-inflates power draw and further reduces system efficiency (η <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">system</sub> ), i.e. the ratio of the useful (margin-free) output power to input power draw.