30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance
Samuel Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong‐Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng‐Fan Chang, Arijit Raychowdhury
Abstract
Tiny surveillance robots need to efficiently compute a perception front-end workload, consisting of a neural network inference stack, and a localization back-end workload implementing a set of state-space equations. Miniaturization and low-power actuation make bristle robots [1] attractive locomotion platforms, but size limits lead to stringent energy constraints. The edge accelerator needs low leakage for long retentive stretches and efficient matrix compute for active bursts. We present a 0.84TOPS/W, 110μW retentive-sleep-capable resistive random-access memory (RRAM)-based accelerator in 40nm with 10 very long instruction word (VLIW)-controlled nonvolatile memory (NVM) matrix units (NMUs) with, in total, 5MB of RRAM, combined with a 10T SRAM-based state-update accelerator enabled by in-place memory updates. At V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</inf> , the design improves NVM access energy to 0.256pJ/b and peak NVM bandwidth to 12.8GB/s.