30-GHz Low-Phase-Noise VCO With Negative Transconductance Optimization in 65-nm CMOS
Alamgir Hossain, Seung Beop Lee, Chul Woo Byeon
Abstract
In this letter, we propose a millimeter-wave low-phase-noise voltage-controlled oscillator (VCO). To enhance the phase noise performance of the VCO without frequency-tuning range (FTR) degradation, a novel negative transconductance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula> ) optimization technique is proposed. This technique utilizes a gate–drain capacitive splitting inductor with a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula> -optimized switching capacitor bank to improve the negative <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula> , phase noise, and FTR performances. Implemented in 65-nm CMOS, the proposed VCO achieves a low phase noise of −107.2 dBc/Hz at a 1-MHz offset, FTR of 28.11–31.46 GHz, and figure-of-merit of −187.6 dBc/Hz at 28.11 GHz with a power consumption of 7.2 mW.