First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles
Yu-Rui Chen, Yi‐Chun Liu, Zefu Zhao, Wan-Hsuan Hsieh, J. H. Lee, Chien-Te Tu, Bo‐Wei Huang, Jer-Fu Wang, Shee-Jier Chueh, Yifan Xing, GuanHua Chen, Hung-Chun Chou, Dong Soo Woo, M. H. Lee, C. W. Liu
Abstract
The large memory window of $1.8\mathrm{~V}$ at the low write voltage of $2\mathrm{~V}$ is achieved by stacked two nanosheet (NS) gate-allaround (GAA) Ge <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.98</inf> Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.02</inf> FeFETs with the channel phosphorus concentration larger than $1\mathrm{E}18\mathrm{~cm}^{-3}$, enabling the erase of GAA FeFET. Isotropic wet etching was used in channel release process. Stacked two NSs have the advantages of reducing cell variation and 2X read current. The stable storage with data retention of $\gt 1\mathrm{E}4$ seconds, linearly extrapolated 10 years, and high endurance $\gt 1\mathrm{E}11$ cycles are also demonstrated. The thermal budget is as low as $400^{\circ}\mathrm{C}$. The stacked NS architecture with high mobility channels makes FeFETs to be compatible with the $2\mathrm{~nm}$ node and beyond.