Design and Qualitative Analysis of Hetero Dielectric Tunnel Field Effect Transistor Device
S. Howldar, B. Balaji, K. Srinivasa Rao
Abstract
A Hetero Dielectric Tunnel field effect transistor with the spacer on both sides of the gate is proposed in this paper. The performance and characteristics of Hetero Dielectric Tunnel field effect transistor using the ATLAS Technology Computer-Aided Design in 5nm regime were analyzed. The band-to-band tunneling leakage current will be reduced by introducing heterojunction and hetero dielectric spacer material in the proposed structure. In Hetero Dielectric Tunnel field effect transistor, double metal gate and high-k dielectric spacer improves high on the current and subthreshold swing. The high-k dielectric Hafnium oxide spacer is placed on both sides of the source and drains to import the tunneling mechanism. The proposed device in the 5nm node has improved DC characteristics such as a High ON-state current of 1.68 x 10-5 Amp & OFF-state Current reduced from 7. 83x 10-11 Amp to 5.13 x 10-12 Amp and ION / IOFF ratio has increased from 3.22 x 105 to 3.27 x 10 compared to conventional dual gate Tunnel field effect transistor. Therefore, this device is suitable for low power applications