A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm<sup>2</sup> in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration
Ioannis A. Papistas, Stefan Cosemans, Bram Rooseleer, Jonas Doevenspeck, M.-H. Na, Arindam Mallik, Peter Debacker, Diederik Verkest
Abstract
Deep learning constitutes the state-of-the-art in machine learning, from data mining to computer vision and natural language processing. Energy-efficient matrix-vector multiplications (MVMs) [1] are key to bringing these capabilities to the edge, for both convolutional and recurrent neural networks. Since low precision multiplications with a limited level of noise can achieve relatively high accuracies [2], a compelling opportunity arises for mixed-signal hardware implementations to exploit in-memory computing paradigms [3- 6]. In this work, a matrix-vector multiplier is presented operating on ternary weights, 7-bit input (6-bit magnitude and 1-bit sign), and 6-bit output activations. Notable improvements in energy efficiency and peak compute throughput per unit area are exhibited by measurements on a test chip based on the GLOBALFOUNDRIES® 22FDX® FD-SOI platform, thanks to a novel SRAM-based compute cell with low “on” current, pulse-width encoded input activations, a clamp-free summation line, and efficient amortization of the ADC and DAC energies.