Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing
W. Hafez, Prashant Agnihotri, M. Asoro, Muratahan Aykol, B. Bains, R. Bambery, Mukund Bapna, Amar Kumar Barik, Avhishek Chatterjee, P. C. Chiu, T. Chu, C. J. Firby, K. Fischer, M. I. Fradkin, Hannes Greve, Arnab Sen Gupta, Erik Haralson, M. Haran, J. Hicks, A. Illa, M. Jang, Sabina Beranič Klopčič, M. Kobrinsky, Brian Kuns, Huaping Lai, G. Lanni, Stanley Lee, N. Lindert, Carol Lo, Yuxuan Luo, Gokul Malyavanatham, B. Marinkovic, Y. Maymon, M. Vernon Nabors, J. Neirynck, P. Packan, Ayushi Paliwal, L. Pantisano, L. Paulson, Padma Penmatsa, C. Prasad, Conor Puls, Tauhidur Rahman, R. Ramaswamy, S Samant, B. Sell, Kanika Sethi, F. Shah, M. Shamanna, Kun Shang, Q. Li, M. Sibakoti, J. Stoeger, Nathan Strutt, R. Thirugnanasambandam, C. Tsai, Xielin Wang, Allen T. Wang, Shin-Rung Wu, Qunwei Xu, Xiaoxiong Zhong, S. Natarajan
Abstract
This paper presents a high-yielding backside power delivery (BPD) technology, PowerVia, implemented on Intel 4 finFET process. PowerVia more directly integrates power delivery to the transistor as compared to published buried power rail schemes, enabling additional wiring resources on front side for signal routing. A fabricated E-core with $\gt 90$% cell utilization showed $\gt 30$% platform voltage droop improvement and 6% frequency benefit compared to a similar design without PowerVia. Transistor performance, reliability, and fault isolation capability is detailed.