Hardware Resource and Computational Density Efficient CNN Accelerator Design Based on FPGA

Xiang Chen, Jindong Li, Yong Zhao

20212021 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)17 citationsDOI

Abstract

Convolutional neural networks (CNNs) have become more and more popular in machine vision tasks, including image classification and object detection. As one of the most promising platforms for accelerating CNNs, Field Programmable Gate Array (FPGA) can achieve a better trade-off between speed, flexibility, cost, and power consumption, thus is more suitable in Edge-AI scenarios, which is generally constrained by cost and power. In this paper, by flexibly using line buffer and tiling, we propose an efficient CNN accelerator design based on FPGA. The implementation results indicate the peak performance of the proposed accelerator can reach 172.8 GOP/s, only occupying 24K LUTs (Look-Up-Table), 40.5 BRAMs (Block Ram), and 296 DSP48s, which shows the highest efficiency of hardware resource and computational density compared with previous works.

Topics & Concepts

Field-programmable gate arrayComputer scienceConvolutional neural networkBlock (permutation group theory)Hardware accelerationFlexibility (engineering)Lookup tableComputer hardwareEnhanced Data Rates for GSM EvolutionTable (database)Embedded systemEdge deviceArtificial intelligenceOperating systemCloud computingGeometryStatisticsMathematicsData miningAdvanced Neural Network ApplicationsCCD and CMOS Imaging SensorsBrain Tumor Detection and Classification