A Dual-Gate Vertical Channel IGZO Transistor for BEOL Stackable 3D Parallel Integration for Memory and Computing Applications
Ziyi Liu, Yiwei Dul, Renrong Liang, Zhigang Zhang, Liyang Pan, Jianshi Tang, Renrong Liang, Bin Gao, Qi Hu, Jun Xu, He Qian, Huaqiang Wu, Yuegang Zhang
Abstract
In this work, we demonstrate a stackable vertical single/dual-gate(SG/DG) C-shaped-channel field-effect transistor (VCCFET) based on atomic layer deposition (ALD) In-Ga-Zn-O thin film with an Ion/loff ratio over I. <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4\times 10^{11}$</tex> and an on current of 21 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu \mathrm{A}/\mu \mathrm{m}$</tex>. And we firstly fabricate vertical dual-gate IGZO transistors, featuring Gate-AlI-Around Lateral Gate (LG) and Channel-AlI-Around Vertical Gate(VG). The dual gates can be biased simultaneously to enhance gate control capability, or bias independently to random access and linearly adjust threshold voltage (Vt). This makes the developed transistor broadly applicable of memory and computing. Also, this device has future prospect for BEOL (≤300°C) 3D parallel integration, where different layers of transistors can be formed concurrently with independent source/drain contacts. And the one-step channel formation approach, akin to 3DNAND, reduces lithography costs and eliminates device performance degradation induced by sequential integration.