Nonvolatile Capacitive Synapse: Device Candidates for Charge Domain Compute-In-Memory
Shimeng Yu, Yuan-Chun Luo, Tae‐Hyeon Kim, Omkar Phadke
Abstract
Compute-in-memory (CIM) has emerged as a compelling approach to address the ever-increasing demand for energy-efficient computing for edge artificial intelligence (AI) applications. Nonvolatile capacitive synapses have been recently proposed to further boost the energy and area efficiency of CIM hardware with the following attractive features when compared with resistive synapses: negligible static power consumption, selectorless access, low interconnect voltage drop and exemption from sneak-path leakage, limited read disturb owing to the small-signal read manner, and great 3D stacking potential. In this article, the operating principle of the capacitive crossbar array for neural network inference is first explained, followed by a survey of state-of-the-art nonvolatile capacitive synapses that are mostly implemented by the ferroelectric devices with asymmetric capacitance–voltage characteristics. Finally, the design guidelines on capacitive device parameters are discussed toward optimizing the array-level performance metrics.