Fast LDPC GPU Decoder for Cloud RAN
Jonathan Ling, Paul Cautereels
Abstract
The graphical processing unit (GPU), as a digital signal processing accelerator for cloud RAN, is investigated. This letter presents a new design for a 5G NR low-density parity check code decoder running on a GPU. The algorithm is flexibly adaptable to GPU architecture to achieve high resource utilization as well as low latency. It improves on the layered algorithm by increasing parallelism on a single code word. The flexible GPU decoder (on a 24 core GPU) was found to have <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times $ </tex-math></inline-formula> higher throughput compared to a recent GPU flooding decoder and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> higher throughput compared to a field programmable gate array (FPGA) decoder (757K gate). The flexible GPU decoder exhibits 1/3 decoding power efficiency of the FPGA typical of general-purpose processors. For rapid deployment and flexibility, GPUs may be suitable as cloud RAN accelerators.