Device performance and strain effect of sub-5 nm monolayer InP transistors
Linqiang Xu, Ruge Quhe, Qiuhui Li, Shiqi Liu, Jie Yang, Jie Yang, Chen Yang, Bowen Shi, Hao Tang, Ying Li, Xiaotian Sun, Jinbo Yang, Jinbo Yang, Jing Lü
Abstract
The performance limit of the sub-5 nm monolayer (ML) indium phosphide (InP) FETs is explored. I on , τ , and PDP of the ML InP FETs could meet the ITRS demands for the high-performance/low-power devices until gate length is reduced to 2/4 nm.
Topics & Concepts
MonolayerMaterials scienceIndium phosphideOptoelectronicsPhosphideTransistorStrain (injury)NanotechnologyGallium arsenideElectrical engineeringVoltageInternal medicineNickelEngineeringMedicineMetallurgyAdvancements in Semiconductor Devices and Circuit DesignNanowire Synthesis and ApplicationsSemiconductor materials and devices