Integrated Modulation of Dual-Parallel NPC Inverters With Eliminated CMV
Weiwei Li, Xueguang Zhang, Dianguo Xu
Abstract
An integrated zero common-mode voltage (ZCMV) modulation algorithm is developed in this article for dual-parallel neutral-point-clamped (NPC) inverters treated as an integrated system. While the conventional methods achieve CMV elimination with the cost of worse harmonic performance, the proposed method guarantees a ZCMV and better current quality simultaneously by taking advantage of the extra space vectors provided by paralleling. Specially designed switching sequences are developed to maintain a balanced neutral point of dc bus and keep the averaged value of the circulating current to be zero, ensuring the normal function of parallel NPC inverters. In addition, although the switching sequence design is complicated, a simple approach is proposed and implemented on a commonly used digital signal processor. A laboratory prototype is developed to test the system performance under steady-state conditions and dynamic process in grid-connected operation. Compared with the conventional ZCMV modulation, experimental results verify the effectiveness of the integrated modulation in eliminating the CMV, in addition to the dramatically reduced output current distortion.