A Dynamic Gate Driver IC with Automated Pattern Optimization for SiC Power MOSFETs
Wen Tao Cui, William Zhang, Jingyuan Liang, Haruki Nishio, Hitoshi Sumida, Hiroyuki Nakajima, Yuan-Ta Hsieh, Hann-Huei Tsai, Ying‐Zong Juang, Wen‐Kuan Yeh, Wai Tung Ng
Abstract
The switching transient of SiC power MOSFETs are often affected by the gate voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GATE</inf> ) swings due to the fast charging/discharging of their gate capacitances. Using a gate resistance (R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> ) can effectively limit the influx of gate current but reduces the switching speed of the transistor. Both factors can be improved using a dynamic gate driving scheme with varying R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> . The optimum timings of the dynamic R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> pattern are dependent on different SiC power MOSFETs and their operating conditions. Previously, a trial-and-error iterative process is required to determine the optimal timing. An automated method to optimize the timings of the dynamic R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> pattern is proposed in this paper. The V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GATE</inf> signal of the SiC power MOSFET is processed internally by an analog circuit and the resultant timing indicator (T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SEG</inf> ) is digitized for feedback through an on-chip TDC. The optimum dynamic gate drive timing T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OPT</inf> is obtained by subtracting T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SEG</inf> from the inherent delay cause by the sensing circuit. The output can be interpreted by an external compensator. A set of digital timing configurations are then fed back to the IC to optimize the dynamic R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> pattern timings for the next switching cycle (T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OPT(n+1)</inf> ). The proposed dynamic gate drive IC can provide ringing suppression while maintaining high switching speed for SiC power MOSFETs automatically.