Vertical Gate-All-Around Device Architecture to Improve the Device Performance for Sub-5-nm Technology
Changwoo Noh, Changwoo Han, Sang Min Won, Changhwan Shin
Abstract
In this work, we propose a vertical gate-all-around device architecture (GAA-FinFET) with the aim of simultaneously improving device performance as well as addressing the short channel effect (SCE). The GAA-FinFET was built using the technology computer-aided design (TCAD) simulation tool, and then, its electrical characteristics were quantitatively evaluated. The electrical characteristics of the GAA-FinFET were compared to those of conventional FinFET and nano-sheet FET (NSFET) at 7 nm or 5 nm nodes. When comparing the GAA-FinFET against the FinFET, it achieved not only better SCE characteristics, but also higher on-state drive current due to its gate-all-around device structure. This helps to improve the ratio of effective drive current to off-state leakage current (i.e., Ieff/Ioff) by ~30%, resulting in an improvement in DC device performance by ~10%. When comparing the GAA-FinFET against the NSFET, it exhibited SCE characteristics that were comparable or superior thanks to its improved sub-channel leakage suppression. It turned out that the proposed GAA-FinFET (compared to conventional FinFET at the 7 nm or 5 nm nodes, or even beyond) is an attractive option for improving device performance in terms of SCE and series resistance. Furthermore, it is expected that the device structure of GAA-FinFET is very similar to that of conventional FinFET, resulting in further improvement to its electrical characteristics as a result of its gate-all-around device structure without significant modification with respect to the processing steps for conventional FinFET.