High-Performance IIR Filter Implementation Using FPGA
Vallabhuni Vijay, V. R. Seshagiri Rao, Kancharapu Chaitanya, S China Venkateshwarlu, Chandra Shaker Pittala, Rajeev Ratna Vallabhuni
Abstract
This document investigation is performed on improved implementation of an Infinite Impulse Response (IIR) filter which can utilized practically. There are many other proposed models for IIR filters that yield promising and efficient results. The suggested IIR filter model known as a parallel-pipeline based on FIR filter. FIR filters on the other hand provide linear phase response, high stability, and limited precision errors. So, FIR based IIR filter offers better efficiency than its previous models. Moreover, there are other techniques such as the Two-Level Pipeline based IIR filter model and look-ahead-based model are mentioned and discussed. And the synthesis and results are obtained on a Xilinx Virtex-5 field-programmable Gate Array Board. After analyzing all design models mentioned, A new model for the implementation IIR filter is discussed which increases the efficiency of the filter.