Energy-Efficient Wide-Range Level Shifter With a Logic Error Detection Circuit
Jihwan Park, Hanwool Jeong
Abstract
In this brief, an energy-efficient, wide-range level shifter (LS) with a logic error detection circuit (LEDC) is proposed. The proposed LS is designed based on a current mirror-based LS (CMLS), and a feedback pFET is added to solve the static current, which is a limitation of the CMLS. Similarly, Wilson’s CMLS (WCMLS) solves the problem of the CMLS through the feedback pFET; however, it cannot convert low supply voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {DDL}}$ </tex-math></inline-formula> ) to high supply voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {DDH}}$ </tex-math></inline-formula> ) fully due to the feedback pFET. In contrast, the proposed LS can convert <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {DDL}}$ </tex-math></inline-formula> to full <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {DDH}}$ </tex-math></inline-formula> using the LEDC. To verify the performance between the proposed LS and the previously proposed LS, the postlayout simulation was performed using the 7-nm finFET model. The simulation results of the proposed LS show that the propagation delay and energy are 0.21 ns and 20.43 fJ, respectively, at a low/high voltage of 0.4/1.2 V and an input frequency of 1 MHz.