Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration
Qiaochu Zhang, Hsiang‐Chun Cheng, Shiyu Su, Mike Shuo‐Wei Chen
Abstract
This article presents a fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> digital multiplying delay-locked loop (MDLL) that uses a digital-to-time converter (DTC) for controlling the reference injection timing to support the fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> operation. This fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> MDLL features an injection-error scrambling scheme for DTC error randomization and a background third-order DTC delay equalizer for DTC error calibration, to mitigate reference-injection-induced spurs while keeping a low phase noise floor. The MDLL prototype demonstrates 800-fs rms jitter, −67 dBc fractional spur, and −58 dBc reference spur. With the proposed schemes, the fractional and reference spurs are suppressed by 29 and 32 dB, respectively.