30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology
Higuchi Tsutomu, Takuyo Kodama, Koji Kato, Ryo Fukuda, Naoya Tokiwa, Mitsuhiro Abe, Teruo Takagiwa, Yuki Shimizu, Junji Musha, Katsuaki Sakurai, Jumpei Sato, Tetsuaki Utsumi, Yoneya Kazuhide, Yasuhiro Suematsu, Toshifumi Hashimoto, Takeshi Hioka, Kosuke Yanagidaira, M. Kojima, Junya Matsuno, Kei Shiraishi, Kensuke Yamamoto, Shintaro Hayashi, Tomoharu Hashiguchi, Kazuko Inuzuka, Akio Sugahara, Mitsuaki Honma, Keiji Tsunoda, Kazumasa Yamamoto, Takahiro Sugimoto, Tomofumi Fujimura, Mizuki Kaneko, Hiroki Date, Osamu Kobayashi, Takatoshi Minamoto, Ryoichi Tachibana, Itaru Yamaguchi, Juan Lee, Venky Ramachandra, Srinivas Rajendra, Tianyu Tang, Siddhesh Darne, Jiwang Lee, Jason Li, Toru Miwa, Ryuji Yamashita, Hiroshi Sugawara, Naoki Ookuma, Masahiro Kano, Hiroyuki Mizukoshi, Yuki Kuniyoshi, Mitsuyuki Watanabe, Kei Akiyama, Hirotoshi Mori, Akira Arimizu, Yoshito Katano, Masakazu Ehama, Maejima Hiroshi, Koji Hosono, Masahiro Yoshihara
Abstract
This work demonstrates a novel 1Tb 3D Flash memory chip that has an area efficiency of 10.4Gb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a 3b/cell technology. Using a circuit under array (CUA) design technique and over 170 word-line (WL) layers, the chip achieves 33% higher bit density than prior 3b/cell work [1], and better density than in 4b/cell technology [3]. This paper discusses the challenges advanced 3D Flash memories face: using over 100 WL layers results in large parasitic loads and decreases read/program speed, and its complicated operation increases test costs. On the other hand, as high bandwidth is also required, this chip supports a 2.0Gbps IO transfer rate, while maintaining signal integrity. This work introduces four new key technologies to address these difficulties. 1) Asynchronous independent plane read (AIPR), with a 4-plane architecture to improve system-level performance. 2) Enhanced sensing that enables faster read time (tR). 3) IO-DCC (duty cycle correction) training for high-speed DDR operation. 4) A scan chain to improve test coverage and cost effectiveness.